1. Field of the Invention
The present invention relates to delay lines, and more particularly, to a delay line with no exit tree that is integrated with a measure initialization path.
2. Description of the Prior Art
A standard DRAM needs to operate according to highly accurate clock timing. Internally generated clock signals are used to perform various operations of the DRAM, wherein the internal signals are generated according to an external clock, which is input to a delay line in the DRAM chip and delayed for a determined amount. In order for the DRAM to operate correctly, the internal (delayed) signals must be synchronous with the external signal; i.e. the rise and fall of both signals must match. Therefore, an amount of delay in the delay line must be precisely determined.
A standard delay line comprises a series of delay elements such as NAND gates, wherein each delay element adds a further amount of delay to the signal. For outputting the delayed signals, some delay lines include a multi-layer exit tree structure, comprising stages of further delay elements coupled to the main (forward) delay line. The addition of these multiple layers means that extra gates are added to the forward delay path, incurring larger Duty Cycle Distortion as well as larger Power Supply Sensitivity.
To solve these issues, other delay lines integrate the exit tree into the delay line, by including common entry points coupled to every NAND cell (delay element). Although this solves the problems of reducing forward path delay incurred by the above-mentioned delay line, large loading is required to power all the common entry points and introduces a new duty cycle and power supply sensitivity node issue.
By merging the exit tree with the delay line, this loading can be reduced, as well as reducing the amount of Duty Cycle Distortion and Power Supply Sensitivity. Please refer to FIG. 1, which is a diagram illustrating a delay line with no exit tree. As shown in the diagram, the delay line 100 consists of a central chain of series linked NAND pairs for receiving an ‘IN’ signal, an OutEven line of series linked NANDs coupled to one NAND pair chain for outputting a delayed signal, and an OutOdd line of series linked NANDs coupled to the other NAND pair chain for outputting a delayed signal. The two output signals are delayed with respect to each other but still need to be synchronized (with plus or minus static phase difference); therefore it is important that both output stages are equally matched in terms of delay.
The disadvantage of the above structure is that it is incompatible with fast measure initialization. Measure initialization is a technique used to set a delay line to a correct delay by establishing a delay amount for each stage, such that an initial starting point or final exit point can be accurately selected for each required delay. When inputting a signal to the delay line, only the last exit point is enabled such that the signal is propagated through all possible stages of the delay line. Both the input and output buffer delays can thereby be determined and the delay line can be set to have a correct initial delay for achieving fast synchronization. The system shown in FIG. 1 can only propagate a signal through one of the output buffer stages (OutOdd or OutEven). It would take a much longer time to have this delay line properly initialized (for instance, a binary search) and the delay line is therefore vulnerable to glitches which cause possible failures. As mentioned above, the signal is tapped at both ‘out’ stages, and if the gates are not identical the OutOdd and OutEven signals may be out of phase.